Intel Sandy Bridge and P67 – Review
Review: Intel P67, Sandy Bridge, and Native SATA
The Intel Sandy Bridge processor architecture has been on the horizon for quite some time, and it seems like ages ago that it was first rumoured. It was known from the outset that the new CPU would have a more advanced architecture than previous Intel CPU’s, it would be based on a 32nm fabrication process, be more powerful, and at the same time consume less power. It would also host a much more capable IGP, and much more advanced multimedia features.
It was back in July that these rumours became a reality, when the first engineering samples of the new processor began to land on tester’s benches. For me, I have to admit I was rather disappointed, not with the processor itself, but the fact that the Sandy Bridge parts would require a new processor socket, and therefore a new motherboard and chipset, the 6 series chipset to be exact. However, once details started to emerge that the mainstream high performance P67 chipset would also host a brand new native 6Gbps SATA host controller; I started to become much more optimistic about the new platform.
P67 is Intel’s second foray into a 2 chip solution, the P55 being the first chipset to do away with the North Bridge chip, and host the memory controller and the x16 PCI Express controller in the CPU package itself, with the South Bridge being renamed to PCH (Platform Controller Hub). In most parts, P55 was a nice mainstream solution, but it most certainly had its limitations. With only 16 PCIe2 lanes for graphics, and a further 8 PCIe2 lanes for the PCH, bandwidth was bound to become an issue for high end two card graphic solutions. It was further compounded by the fact that although P55 had PCIe2, these lanes were half duplex, meaning although a single lane had 5Gbps of concurrent bandwidth, in reality it was half of this in the real world (2.5Gbps), as the bandwidth was shared between send and receive.
Sandy Bridge and P67 is altogether different. It still has 16 PCIe2 lanes for graphics and 8 PCIe2 lanes for the PCH at 5Gbps, but this time these run at full duplex, which means there is actually 10Gbps of concurrent bandwidth.
In this article I will be taking a brief look at the Sandy Bridge platform itself, and a more in depth look at the P67 PCH in regards to SATA storage performance.
This article had been completed before the P67 SATA flaw had been announced by Intel. However, after careful consideration, I decided to publish the article, as I think from the obtained results, there is no evidence of the review system used in this article having been affected by the flaw in the P67 chipset.
Let’s head to the next page where we will take a closer look at the Sandy Bridge platform…..