The numbers of layers in 3D NAND flash memory will increase to 140 or more by 2021, according to a road map from Applied Materials that was presented during the International Memory Workshop in Kyoto, Japan. Besides adding more layers, manufacturers also try to make the layers thinner.
The benefit of 3D NAND compared to 2D NAND is that it’s possible to store more data on the same chip area. With 2D NAND the data capacity could only be increased by making cells smaller, fit more bits per cell or increase the chip size. 3D NAND adds another possibility of increasing data capacity, adding height to the chips, by stacking layers.
This year, Toshiba and Western Digital are expected to mass produce 96-layer BiCS 3D NAND. Also, the fifth generation 3D NAND from Samsung should reach 96 layers this year. By 2020 most NAND manufacturers should be able to produce 3D NAND with about 120 layers and Applied Material expects that by 2021 the number of layers will increase to about 140. The 140 layers will be possible due to the use of new materials.
Together with the increase in the number of layers, all layers will also become thinner. That means the height of chips will not scale linearly with the number of layers. Layers are now about 55 nm each, by 2021 this should be about 45 nm.
Applied Material’s road map doesn’t state anything about the actual data capacity increase of the technology improvements. However, Samsung previously announced it aims for chips with a capacity of 1 terabit. The increased data density is possible by using four-bits-per-cell (QLC) and 96 layers. Currently, 64 layer technology provides chips with 512 gigabits.
The road map comes from Applied Materials, an American company that supplies equipment, services and software for semiconductor chip manufacturing.