Toshiba, today announced that it has developed a prototype sample of 96-layer BiCS 3D flash memory with a stacked structure, with 3-bit-per-cell (triple-level cell, TLC) technology. Samples of the new 96-layer product, which is a 256 gigabit (32GB) device, are scheduled for release in the second half of 2017 and mass production is targeted for 2018.
Going forward, Toshiba Memory Corporation will apply its new 96-layer process technology to larger capacity products, such as 512 gigabit (64 gigabytes) and 4-bit-per-cell (quadruple-level cell, QLC) technology, in the near future.
The 96-layer stacking process combines with advanced circuit and manufacturing process technology to achieve a capacity increase of approximately 40% per unit chip size over the 64-layer stacking process. It reduces the cost per bit, and increases the manufacturability of memory capacity per silicon wafer.
Since announcing the prototype 3D flash memory technology in 2007, Toshiba Memory Corporation has continued to advance development of 3D flash memory and is actively promoting BiCS FLASH to meet demand for larger capacities with smaller die sizes.
This 96-layer BiCS FLASH will be manufactured at Yokkaichi Operations in Fab 5, the new Fab 2, and Fab 6, which will open in summer 2018.
Toshiba's memory division is currently for sale, whether the chips will still come out of a factory with Toshiba on the wall in 2018, is very unlikely.
